About Courses

This training is completely dedicated to provide thorough understanding of all advanced VLSI concepts, fortified through detailed analysis of synthesis, simulation using specially designed reference code. Robust RTL design and advanced verification techniques towards enhancing the reliability, performance and area that are key factors towards building a successful career in the VLSI domain. Hands-on labs, mini/major projects dedicated towards developing a systematic design and verification approach. Basic RTL synthesis and gate level netlist schematic analysis sessions which help in developing a hardware implementation perspective on top of HDL. Thorough understanding of how to convert gate level netlist in to MOS transistor level with detailed explanation of fabrication process.